The present invention relates to MOS type solid-state imaging apparatus having a variable amplification function.
In recent years, MOS (Metal Oxide Semiconductor) type solid-state imaging apparatus are drawing attention. The construction of such prior-art solid-state imaging apparatus and its timing of operation for reading signal will be described below with reference to one disclosed in Japanese Patent Application Laid-Open 2007-19580. FIG. 1 is a conceptual drawing showing the construction of the solid-state imaging apparatus disclosed in the publication. The solid-state imaging apparatus according to this prior-art example includes: a pixel section having pixels 1 arranged into a matrix from which electrical signal corresponding to amount of light incident in a predetermined period is outputted; vertical signal lines 3 through which signals from the pixel section are read out by the unit of row; a vertical scanning section 2 for inputting control signals by the unit of row to the pixel section; noise suppressing sections 4 connected to the vertical signal lines 3 respectively, to suppress noise components contained in signal from the pixel section; a hold capacitor CH for retaining signal after the noise suppression; horizontal signal line read switches MH for sequentially reading out the signal retained at the hold capacitors CH to a horizontal signal line 6; a horizontal scanning section 5 for supplying horizontal select pulses φH1 to φH2 to the horizontal signal line read switches MH; a horizontal signal line reset switch MR for resetting an electric potential on the horizontal signal line 6 to a horizontal signal line reset voltage VR; an output amplifier 7 for amplifying the potential on the horizontal signal line 6 by a predetermined amplification factor; and a timing control section 8 for supplying a horizontal reset control pulse φHR to the horizontal signal line reset switch MR and for supplying control pulses to the vertical scanning section 2, the noise suppressing section 4, and the horizontal scanning section 5.
FIG. 2 is a timing chart showing an operation of the prior-art solid-state imaging apparatus shown in FIG. 1. Shown here is the timing at which pixel signals after noise suppression accumulated at the hold capacitors CH are read out to the horizontal signal line 6. At first, the horizontal reset control pulse φHR is driven to H level to reset the horizontal signal line 6 to the horizontal signal line reset voltage VR. Then, after bringing the horizontal reset control pulse φHR to L level, the horizontal select pulse φH1 is driven to H level to read the pixel signal retained at the hold capacitor CH of the first column to the horizontal signal line 6. It is assumed here that the larger the pixel signal the lower the potential on the horizontal signal line 6. Next, after bringing the horizontal select pulse ?H1 to L level, the horizontal reset control pulse φHR is driven to H level again to reset the horizontal signal line 6. Then, after bringing the horizontal reset control pulse φHR to L level, the horizontal select pulse φH2 is driven to H level to read the pixel signal retained at the hold capacitor CH of the second column to the horizontal signal line 6. By repeating control in this manner, the signals on each column are sequentially read out to the horizontal signal line 6. The pixel signals read out to the horizontal signal line 6 are amplified by a predetermined amplification factor at the output amplifier 7 and then are outputted.
The operation for reading pixel signal to the hold capacitor CH for example may be an operation with the pixel construction and the construction of the noise suppressing section as shown in FIGS. 3A and 3B. As shown in FIG. 3A, each pixel 1 includes: a photodiode PD for changing an incident light into an electrical signal; a transfer transistor M1 for transferring the electrical signal accumulated at the photodiode PD; an amplification transistor M3 for amplifying the transferred electrical signal; a reset transistor M2 for resetting an electric potential for example of an gate electrode of the amplification transistor M3; and a row select transistor M4 for selectively outputting amplified signal based on the electrical signal. A transfer pulse φTX, a reset pulse φRST, and a row select pulse φROW are inputted by the unit of row from the vertical scanning section 2 respectively to the gate of the transfer transistor M1, the reset transistor M2, and the row select transistor M4. Further, a pixel power supply VDD is connected to the drain of the reset transistor M2 and the amplification transistor M3.
The noise suppressing section 4 as shown in FIG. 3B includes: a bias transistor M5 for flowing a constant current to the vertical signal line 3; a clamp capacitor CL and clamp transistor M7 for clamping pixel signal; and a sample-and-hold transistor M6 for retaining signal after noise suppression. A clamp pulse φCL is supplied to the gate of the clamp transistor M7, and a sample-and-hold pulse φSH to the gate of the sample-and-hold transistor M6. Further, a bias voltage VBIAS is supplied to the gate of the bias transistor M5, and a clamp voltage VC to the drain of the clamp transistor M7.
FIG. 4 is a timing chart for showing operation for reading signal of the pixel section constructed as in FIG. 3A and the noise suppressing operation by the noise suppressing section constructed as in FIG. 3B. At first, the row select pulse φROW is driven to H level whereby a portion of the pixel section corresponding to one row is selected and signals of the selected row are read out to the vertical signal line 3. Next, the reset pulse φRST is driven to H level to reset the gate potential of the amplification transistors M3 of the selected row whereby the reset potential of pixel is outputted to the vertical signal line 3. At this time, the sample-and-hold pulse φSH is maintained at H level and the clamp pulse φCL at H level at the noise suppressing section 4 so as to connect the noise suppressing section 4 to the vertical signal line 3 and at the same time to clamp an output of the noise suppressing section 4 to the clamp potential VC.
Next, after completing reset of each pixel 1 by bringing the reset pulse φRST to L level, the clamp pulse φCL is brought to L level to end the clamping operation at the noise suppressing section 4. Next, the transfer pulse φTX is driven to H level so that signal electric charges generated in a predetermined period at the photodiode PD are transferred to the gate of the amplification transistor M3.
A signal potential corresponding to signal electric charges generated at the photodiode PD is thereby outputted to the vertical signal line 3, and, even when the transfer pulse φTX is brought to L level, signal potential corresponding to signal electric charges generated at the photodiode PD is continuously outputted to the vertical signal line 3. At this time, the output of the noise suppressing section 4 is changed from the clamp potential VC corresponding to a change from the reset potential to the signal potential of the pixel 1. The noise components contained in the reset potential and the signal potential are thereby subtracted. Finally, the noise suppressing operation is completed by bringing the sample-and-hold pulse φSH to L level, and then the row select pulse φROW is brought to L level to electrically disconnect the selected row from the vertical signal line 3.
The reading of pixel signal and the noise suppressing operation are rendered as the above so that pixel signal after noise suppression is retained at the hold capacitor CH.